Some integrated circuits are required to undergo high voltage testing prior to packaging. In many situations, the testing is performed at the wafer level in order to identify defective integrated circuits on the wafer before they are processed into individual packages. The testing may involve the use of a wafer prober that includes a first probe and a second probe. The probes contact specific portions of the wafer and then apply a voltage potential between the first probe and the second probe.
Integrated circuits located on the wafer are very small, so the first probe and the second probe are typically very close to each other. The close proximity of the first probe to the second probe may cause problems during the high voltage tests, and even low voltage tests. For example, humidity or condensation on the wafer or the wafer probes may cause a slight current flow between the first probe and the second probe, which is referred to as leakage. The leakage reduces the voltage potential between the first probe and the second probe, so the integrated circuits on the wafer are not subjected to the intended high voltage.
Currently, high voltage testing of wafers is conducted in an environmentally controlled chamber in the wafer prober. The wafer is placed in the chamber and electrically connected to a test card. The chamber is filled with a gas, such as nitrogen, to dry the wafer and the test card. After a period, which is commonly as long as twenty minutes, the wafer and the test card are assumed to be dry and the wafer is tested. This procedure is very time consuming.